1. Field of the Invention
The present invention pertains to solid state memory fabrication and more particularly to fabrication of DRAM chips with self alignment of field plate/BL isolation process by using one step oxide-polysilicon-oxide etch followed by oxidation or sidewall deposition (LPTEOS) to isolate the field plate and BL.
2. Related Prior Art
Prior art has several processes for the manufacture of polysilicon CMOS DRAM chips. In fact, most present day DRAM chips, (Dynamic Random Access Memory), use CMOS or Complementary Metal Oxide Semiconductor technology. Although the term CMOS has a definite meaning, CMOS technology has been applied to any integrated circuit which uses N-channel and P-channel field effect transistors in a complementary manner.
CMOS integrated circuit devices are often referred to as semiconductor devices, however, these devices are fabricated from various materials that are either electrically conductive, nonconductive or semiconductive. Silicon is the most commonly used semiconductor and may be made conductive by doping its elementary crystalline structure with impurities such as boron or arsenic or phosphorus, each having one less or one more valence electron in its outer electron level. Depending on whether one less electron or one more electron is added, the semiconductor will be either P-type material (one less electron) or N-type material (one more electron).
Silicon may be used in either single crystal form or polycrystalline form. Polycrystalline silicon is often referred to as polysilicon. Polysilicon has been used extensively for gates in field effect transistors but is augmented in some instances. When operation speed is a factor, metal with its inherent high conductivity is used to provide a speed increase. This is usually done by placing a layer of refractory metal silicide on the transistor gates to increase speed through high conductivity.
Initially, the CMOS DRAM process begins with a lightly doped P-type or N-type substrate. Subsequently, several, as many as twelve or more, photo resist masking steps take place in the manufacturing process prior to siliciding source and drain regions on the DRAM chip. One representative method of manufacture is described in the U.S. patent described below.
U.S. Pat. No. 5,026,657, titled "Split-Polysilicon CMOS DRAM Process Incorporating Self-Aligned Silicidation Of The Cell Plate, Transistor Gates, and N.sup.+ Regions", issued to R. Lee et al., is for a split-polysilicon CMOS DRAM process which incorporates a self-aligned silicidation of the cell plate, transistor gates and N.sup.+ regions. By employing a light oxidation step to protect the P-channel transistor sidewall gates from silicidation during a subsequent processing step, the proposed process purports to avoid the problems that may be created by the double etching of the field oxide and active area regions that is required for self-aligned silicidation utilizing a split-polysilicon CMOS process. A protective nitride layer is used to prevent oxidation on those regions which are to be silicided. When this improved process is utilized for DRAM fabrication, the protective nitride layer may also be utilized as the cell dielectric. Although this process precludes the silicidation of the sources and drains of P-channel transistors, silicidation of other important regions is accomplished with very few steps required beyond those required for the basic split-polysilicon CMOS process without self-aligned silicidation of conductive regions.
Referring initially to FIGS. 1 and 2, a plan view of the layout of a typical DRAM chip 12 is illustrated as having 2P area 14, 2C area 16 and 3P window 18 in 3P deposition 20 (see FIG. 2). When design rules become more stringent, the techniques of self-alignment become more useful and critical. In the conventional method, the overlap between the field plate Poly-3 (or 3P) window 18 and the BL/N.sup.+ contact area 2C 16 will limit the planar area (or the X.sup.-1 sectional area) of the storage node Poly-2 14 due to the design rule between the Poly-3 window 18 and the Poly-2 node 14. Therefore, if the self-alignment techniques can be applied on the Poly-3/BL, then the planar area of Poly-2 node 14 can be increased and subsequently, capacitance can be increased. The isolation between Poly-3 and BL can be achieved by oxidation or sidewall deposition (LPTEOS) as illustrated in FIG. 4 to gain electrical insulation. Furthermore, the design rule between the Poly-3/BL is no longer required and the area of Ploy-2 can be increased to increase the capacitance.
For example, using a 0.45 .mu.m DRAM, the area of Poly-2 is limited by the overlap between 3P deposition 20 and 2P node 14 and the overlap between 2C (BL/N.sup.+ contact) and 3P window. In a 0.45 DRAM, 3P-2P overlap is equal to 0.212 .mu.m and the 2C-3P overlap is equal to 0.273 .mu.m. When the dimension of the mask CD shrinks even smaller through processing, the area of 2P is also reduced. Therefore, one condition to allow for mask shrinkage is to increase the area of the 2P node 14.
Using the reduction to 0.38 .mu.m due to shrinkage as an example, the original capacitance is 25 pf (for a 0.45 .mu.m DRAM). If the memory shrinks to a 0.38 .mu.m DRAM, then the 2P area will correspondingly become smaller and the capacitance will become smaller to a value less then 18 pf. Therefore, in order to maintain the standard capacitance, the 2P area must be increased. However, the 2P area is limited in a conventional manufacturing process due to consideration of the required overlap of 3P-2P and 2C-3P.